Document Type


Date of Degree

Fall 2014

Degree Name

PhD (Doctor of Philosophy)

Degree In

Electrical and Computer Engineering

First Advisor

Sudhakar M. Reddy

Second Advisor

Janusz Rajski


Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.

At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.

We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.

In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced

by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.

Public Abstract

Test set size is known to increase at a faster rate than device size. Test cost for a given circuit is directly proportional to the number of independent test data inputs called test vectors, hence reducing the number of test vectors reduces test cost. Automatic Test Pattern Generation (ATPG), a tool, used to generate test patterns is used to generate tests. Decisions made while generating tests play an important role and should be made in a manner to facilitate detection of undetected faults. Since, modern design use compression logic –a mechanism in which only a given number of deterministically specified positions can be encoded, reduction in the number of specified positions is a necessity.

We first propose new heuristics for making ATPG decisions based on undetected faults. The heuristics presented create appropriate balance between two contradictory requirements of allowing a test to facilitate detection of undetected faults and the number of specified positions in tests. Further, we propose an ATPG methodology to reduce test set sizes when additional hardware is used to improve test pattern counts. Next we propose a new fault ordering scheme based on ease of detection of a fault which also aids in reducing test pattern counts.

When a chip is tested, usually power dissipation is more than functional specifications leading to over-stressing of tested chips, potentially causing damage to chips during test. W


publicabstract, ATPG, Compaction, Compression, Decision Algorithms, Low Power


xiv, 141 pages


Includes bibliographical references (pages 132-141).


Copyright 2014 Amit Kumar